Development of high speed integrated circuit for very high resolution timing measurements
Development of high speed integrated circuit for very high resolution timing measurements
Dokument öffnen (820.9KB)Art der Hochschulschrift
DissertationPrüfungsdatum
22.10.2009Datum der Veröffentlichung
07.12.2009Erstgutachter
Moreira, Paulo Rodrigues S.Zweitgutachter
Wermes, NorbertMetadaten
Zur Langanzeige
Zitierbare Links 
Inhalt
A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described.
The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption.
The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption.
Schlagwörter
ASIC, Anwendungsspezifische integrierte Schaltung, TDC, Time to digital converter, LHC, Teilchenbeschleuniger, Europäische Organisation für Kernforschung
Klassifikation (DDC)
500 Naturwissenschaften 530 Physik 600 Technik 620 Ingenieurwissenschaften und MaschinenbauMester, Christian: Development of high speed integrated circuit for very high resolution timing measurements. - Bonn, 2009. - Dissertation, Rheinische Friedrich-Wilhelms-Universität Bonn.
Online-Ausgabe in bonndoc: https://nbn-resolving.org/urn:nbn:de:hbz:5N-19634
Online-Ausgabe in bonndoc: https://nbn-resolving.org/urn:nbn:de:hbz:5N-19634
@phdthesis{handle:20.500.11811/4167,
urn: https://nbn-resolving.org/urn:nbn:de:hbz:5N-19634,
author = {{Christian Mester}},
title = {Development of high speed integrated circuit for very high resolution timing measurements},
school = {Rheinische Friedrich-Wilhelms-Universität Bonn},
year = 2009,
month = dec,
note = {A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described.
The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption.},
url = {https://hdl.handle.net/20.500.11811/4167}
}
urn: https://nbn-resolving.org/urn:nbn:de:hbz:5N-19634,
author = {{Christian Mester}},
title = {Development of high speed integrated circuit for very high resolution timing measurements},
school = {Rheinische Friedrich-Wilhelms-Universität Bonn},
year = 2009,
month = dec,
note = {A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described.
The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption.},
url = {https://hdl.handle.net/20.500.11811/4167}
}
Die folgenden Nutzungsbestimmungen sind mit dieser Ressource verbunden:
