The Faculty of Mathematics and Natural Sciences: Search
Now showing items 1-6 of 6
Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization
(2019-06-14)
In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge ...
Dynamic Local Usage in BonnRouteGlobal
(2023-12-14)
In this dissertation we consider the global routing problem which is a central task in chip design. Up to millions of sets of pins on a chip, so called nets, have to be connected through wires without intersecting each ...
Global Timing Optimization in Chip Design
(2021-04-12)
In this thesis, we aim at solving the interconnect optimization problem comprehensively. By balancing global timing, routing, placement, and power constraints in a global model, we obtain solutions which outperform the ...
Improved Cardinality Bounds for Rectangle Packing Representations
(2019-05-29)
Axis-aligned rectangle packings can be characterized by the set of spatial relations that hold for pairs of rectangles (west, south, east, north). A representation of a packing consists of one satisfied spatial relation ...
Efficient Algorithms for Routing a Net Subject to VLSI Design Rules
(2020-12-17)
In this thesis we consider detailed routing, an important step in the design of integrated circuits. On large instances detailed routing requires packing millions of node-disjoint Steiner trees into a graph with hundreds ......
Interconnect Optimization in Chip Design
(2024-08-12)
In this thesis, we take a closer look at the buffering problem. We review the literature on the buffering problem and examine how different algorithms try to solve it. We present an overview over the different aspects that ...








