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Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization 

Scheifele, Rudolf (2019-06-14)
In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge ...
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Global Timing Optimization in Chip Design 

Daboul, Siad (2021-04-12)
In this thesis, we aim at solving the interconnect optimization problem comprehensively. By balancing global timing, routing, placement, and power constraints in a global model, we obtain solutions which outperform the ...

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AuthorDaboul, Siad (1)Scheifele, Rudolf (1)SubjectResource-Sharing (2)
Signallaufzeiten (2)
Steiner-Bäume (2)
VLSI-Design (2)
Approximationsalgorithmen (1)Global Routing (1)incremental routing (1)Inkrementelles Routing (1)path search (1)Pfadsuche (1)... View MoreClassification (DDC)
510 Mathematik (2)
... View MoreResource TypeDissertation oder Habilitation (2)... View MoreDate Issued2019 (1)2021 (1)

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