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Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization 

Scheifele, Rudolf (2019-06-14)
In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge ...
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Efficient Algorithms for Routing a Net Subject to VLSI Design Rules 

Ahrens, Markus (2020-12-17)
In this thesis we consider detailed routing, an important step in the design of integrated circuits. On large instances detailed routing requires packing millions of node-disjoint Steiner trees into a graph with hundreds ......

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AuthorAhrens, Markus (1)Scheifele, Rudolf (1)Subjectpath search (2)Pfadsuche (2)
Steiner trees (2)
VLSI-Design (2)
design rules (1)Design-Regeln (1)Global Routing (1)incremental routing (1)Inkrementelles Routing (1)Kürzeste Wege (1)... View MoreClassification (DDC)
510 Mathematik (2)
... View MoreResource TypeDissertation oder Habilitation (2)... View MoreDate Issued2019 (1)2020 (1)

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