Front-End Readout Circuit Design for DEPFET Pixel Detectors in 65-nm CMOS

Abstract

This work presents a differential readout integrated circuit for DEPFET pixel matrices, with a systematic evaluation of trade-offs among key performance metrics such as power consumption, noise, and silicon area. Each readout channel integrates a cascode transimpedance amplifier followed by a compact single-ended-to-differential conversion stage, optimized to fully drive the input range of a high-speed, low-power analog- to-digital converter (ADC). The proposed readout architecture is designed in an advanced 65-nm CMOS technology and is designed to interface seamlessly with such ADCs, enabling a system that meets stringent constraints on power density and pixel pitch while delivering the precision required for future high-rate, high-resolution experiments. The circuit targets DEPFET matrices operated in rolling-shutter mode, supporting a minimum input current of 2 <em>µ</em>A and a signal range of interest extending up to 8 <em>µ</em>A (4 MIPs about 20,000 electrons). The readout operates with a total power consumption of 900 <em>µ</em>W per channel and an input-referred noise of 80 nA, corresponding to approximately 200 electrons. The achieved noise performance ensures a comfortable signal-to-noise margin across the full dynamic range.