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Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization
(2019-06-14)
In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge ...
Improved Cardinality Bounds for Rectangle Packing Representations
(2019-05-29)
Axis-aligned rectangle packings can be characterized by the set of spatial relations that hold for pairs of rectangles (west, south, east, north). A representation of a packing consists of one satisfied spatial relation ...
Timing-Driven Macro Placement
(2019-03-29)
Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given ...
Algorithms for Cell Layout
(2019-04-30)
Cell layout is a critical step in the design process of computer chips. A cell is a logic function or storage element implemented in CMOS technology by transistors connected with wires. As each cell is used many times on ...
Topological and Piecewise Linear Pseudoisotopy Functors
(2019-05-16)
We construct two functors Pstrict∂:Top →Top and ℙstrict∂:Top → Spectra such that for a compact manifold M the space P