Cell Layout Routing

Abstract

The design of modern computer chips is an immensely complex task that is typically broken down into many subproblems. One of these is the cell layout problem, which is the task of generating a layout for a given input schematic. A schematic, as displayed in fig. 1.1.1, describes a set of transistors and their interconnections, which are called nets. The goal now is to generate a corresponding layout, which is an instruction of how to physically implement the circuit on the chip. A cell layout is given by a set of rectilinear shapes, all associated to a specific layer (see fig. 1.1.2). These shapes indicate either the positions and properties of the transistors or describe the small metal wires that are to be created during the lithographic manufacturing process to physically realize the nets. During the further steps of the chip design process, this layout will be instantiated many times throughout the chip. <br /> Cell layouts are created for a certain manufacturing process, also called a technology node. Due to physical limitations and the extreme complexity of the manufacturing process, the shapes that make up a cell layout must adhere to a wealth of restrictions referred to as design rules. For example, design rules govern spacing requirements between shapes on the same layer, which prevent shorts in the resulting physical circuit. Modern technology nodes typically come with a design rule manual that defines dozens to hundreds of design rules for each layer. Throughout the lifetime of a technology node, design rules are sometimes updated, e.g. because experiments have shown that some design rules can be relaxed without causing problems during manufacturing. <br /> The cell layout problem is subject to a multitude of concurrent objective functions, which further increase its complexity. Typically, cell layouts should be optimized for size and timing characteristics, but should also take into account e.g. electromigration and soft design rules that increase yield if obeyed, but do not have to be fulfilled at all costs.