Near-Optimum Circuits for Binary Addition and Multi-Output And Functions
Near-Optimum Circuits for Binary Addition and Multi-Output And Functions
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DissertationDate of Exam
17.04.2026Date of Publication
17.06.2026Advisor
Held, StephanCo-Referee
Vygen, JensMetadata
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Abstract
In this thesis we present theoretical and practical work on the optimization of Boolean functions in chip design. On a chip, complex Boolean functions are built from basic building blocks computing for example an AND. For every function there are various possible implementations differing in depth or size. The goal of this thesis is to find a good implementation for special classes of such functions.
The first main chapter is dedicated to the task of adding two binary encoded numbers. This problem can be reduced to the computation of the carry bits, each of which corresponds to a path consisting of alternating AND and OR gates. We derive an algorithm to restructure AND-OR paths, achieving the best depth known so far. The basis for this algorithm are recursive splits similar to those proposed in earlier work. We refine their analysis to derive an improved depth bound of log2 n + log2 log2 n for AND-OR paths with n inputs and refine our bound asymptotically even further. We show that our circuits can be built with a linear number of gates upper bounded by 2.7n by using small multi-output AND functions. Moreover, we show how to use these AND-OR paths to build only slightly deeper adder circuits, i.e., all carry bits, still maintaining linear size. This yields the fastest linear size adders known so far. This chapter is joint work with Ulrich Brenner.
Next, we study the problem of constructing multi-output AND functions with minimum size. Let k be the maximum number of inputs that are combined in a single AND function. We show that the problem is already APX-hard for k = 3. We derive approximation algorithms achieving an approximation guarantee of 1.212 and 1.731 for k = 3 and k = 4, respectively. In both cases we provide a combinatorial algorithm and a randomized LP rounding algorithm. Moreover, we give a 2/3 k algorithm for general k.
Last, we consider the problem of multi-output AND or XOR function optimization on practical instances. We decompose the whole chip into gates with two inputs and apply De Morgan rules to make it consist of ANDs, XORs and inverters only. We then collect single-output AND and single-output XOR functions implemented on the chip and combine them to a larger instance whenever they share at least two inputs. Afterward, we introduce an integer linear program similar to the rounded LP introduced in our theoretical work and solve it using an ILP solver to decrease the number of gates in the instances. This algorithm is then followed by a technology mapping and some other restructuring routines. We present tests on the EPFL logic benchmark instances as well as on industry chips provided by our industry partner IBM and show experimental results and different statistics. Even though there is some distortion by technology mapping, the results show that our core algorithm is useful and can reduce the number of gates significantly.
The first main chapter is dedicated to the task of adding two binary encoded numbers. This problem can be reduced to the computation of the carry bits, each of which corresponds to a path consisting of alternating AND and OR gates. We derive an algorithm to restructure AND-OR paths, achieving the best depth known so far. The basis for this algorithm are recursive splits similar to those proposed in earlier work. We refine their analysis to derive an improved depth bound of log2 n + log2 log2 n for AND-OR paths with n inputs and refine our bound asymptotically even further. We show that our circuits can be built with a linear number of gates upper bounded by 2.7n by using small multi-output AND functions. Moreover, we show how to use these AND-OR paths to build only slightly deeper adder circuits, i.e., all carry bits, still maintaining linear size. This yields the fastest linear size adders known so far. This chapter is joint work with Ulrich Brenner.
Next, we study the problem of constructing multi-output AND functions with minimum size. Let k be the maximum number of inputs that are combined in a single AND function. We show that the problem is already APX-hard for k = 3. We derive approximation algorithms achieving an approximation guarantee of 1.212 and 1.731 for k = 3 and k = 4, respectively. In both cases we provide a combinatorial algorithm and a randomized LP rounding algorithm. Moreover, we give a 2/3 k algorithm for general k.
Last, we consider the problem of multi-output AND or XOR function optimization on practical instances. We decompose the whole chip into gates with two inputs and apply De Morgan rules to make it consist of ANDs, XORs and inverters only. We then collect single-output AND and single-output XOR functions implemented on the chip and combine them to a larger instance whenever they share at least two inputs. Afterward, we introduce an integer linear program similar to the rounded LP introduced in our theoretical work and solve it using an ILP solver to decrease the number of gates in the instances. This algorithm is then followed by a technology mapping and some other restructuring routines. We present tests on the EPFL logic benchmark instances as well as on industry chips provided by our industry partner IBM and show experimental results and different statistics. Even though there is some distortion by technology mapping, the results show that our core algorithm is useful and can reduce the number of gates significantly.
Subjects
Boolean Circuits, Approximation Algorithms, Chip Design, Logic Optimization
Classification (DDC)
510 MathematikRelated Publications
arXiv:2401.03263Armbruster, Susanne: Near-Optimum Circuits for Binary Addition and Multi-Output And Functions. - Bonn, 2026. - Dissertation, Rheinische Friedrich-Wilhelms-Universität Bonn.
Online-Ausgabe in bonndoc: https://nbn-resolving.org/urn:nbn:de:hbz:5-89871
Online-Ausgabe in bonndoc: https://nbn-resolving.org/urn:nbn:de:hbz:5-89871
@phdthesis{handle:20.500.11811/14213,
urn: https://nbn-resolving.org/urn:nbn:de:hbz:5-89871,
author = {{Susanne Armbruster}},
title = {Near-Optimum Circuits for Binary Addition and Multi-Output And Functions},
school = {Rheinische Friedrich-Wilhelms-Universität Bonn},
year = 2026,
month = jun,
note = {In this thesis we present theoretical and practical work on the optimization of Boolean functions in chip design. On a chip, complex Boolean functions are built from basic building blocks computing for example an AND. For every function there are various possible implementations differing in depth or size. The goal of this thesis is to find a good implementation for special classes of such functions.
The first main chapter is dedicated to the task of adding two binary encoded numbers. This problem can be reduced to the computation of the carry bits, each of which corresponds to a path consisting of alternating AND and OR gates. We derive an algorithm to restructure AND-OR paths, achieving the best depth known so far. The basis for this algorithm are recursive splits similar to those proposed in earlier work. We refine their analysis to derive an improved depth bound of log2 n + log2 log2 n for AND-OR paths with n inputs and refine our bound asymptotically even further. We show that our circuits can be built with a linear number of gates upper bounded by 2.7n by using small multi-output AND functions. Moreover, we show how to use these AND-OR paths to build only slightly deeper adder circuits, i.e., all carry bits, still maintaining linear size. This yields the fastest linear size adders known so far. This chapter is joint work with Ulrich Brenner.
Next, we study the problem of constructing multi-output AND functions with minimum size. Let k be the maximum number of inputs that are combined in a single AND function. We show that the problem is already APX-hard for k = 3. We derive approximation algorithms achieving an approximation guarantee of 1.212 and 1.731 for k = 3 and k = 4, respectively. In both cases we provide a combinatorial algorithm and a randomized LP rounding algorithm. Moreover, we give a 2/3 k algorithm for general k.
Last, we consider the problem of multi-output AND or XOR function optimization on practical instances. We decompose the whole chip into gates with two inputs and apply De Morgan rules to make it consist of ANDs, XORs and inverters only. We then collect single-output AND and single-output XOR functions implemented on the chip and combine them to a larger instance whenever they share at least two inputs. Afterward, we introduce an integer linear program similar to the rounded LP introduced in our theoretical work and solve it using an ILP solver to decrease the number of gates in the instances. This algorithm is then followed by a technology mapping and some other restructuring routines. We present tests on the EPFL logic benchmark instances as well as on industry chips provided by our industry partner IBM and show experimental results and different statistics. Even though there is some distortion by technology mapping, the results show that our core algorithm is useful and can reduce the number of gates significantly.},
url = {https://hdl.handle.net/20.500.11811/14213}
}
urn: https://nbn-resolving.org/urn:nbn:de:hbz:5-89871,
author = {{Susanne Armbruster}},
title = {Near-Optimum Circuits for Binary Addition and Multi-Output And Functions},
school = {Rheinische Friedrich-Wilhelms-Universität Bonn},
year = 2026,
month = jun,
note = {In this thesis we present theoretical and practical work on the optimization of Boolean functions in chip design. On a chip, complex Boolean functions are built from basic building blocks computing for example an AND. For every function there are various possible implementations differing in depth or size. The goal of this thesis is to find a good implementation for special classes of such functions.
The first main chapter is dedicated to the task of adding two binary encoded numbers. This problem can be reduced to the computation of the carry bits, each of which corresponds to a path consisting of alternating AND and OR gates. We derive an algorithm to restructure AND-OR paths, achieving the best depth known so far. The basis for this algorithm are recursive splits similar to those proposed in earlier work. We refine their analysis to derive an improved depth bound of log2 n + log2 log2 n for AND-OR paths with n inputs and refine our bound asymptotically even further. We show that our circuits can be built with a linear number of gates upper bounded by 2.7n by using small multi-output AND functions. Moreover, we show how to use these AND-OR paths to build only slightly deeper adder circuits, i.e., all carry bits, still maintaining linear size. This yields the fastest linear size adders known so far. This chapter is joint work with Ulrich Brenner.
Next, we study the problem of constructing multi-output AND functions with minimum size. Let k be the maximum number of inputs that are combined in a single AND function. We show that the problem is already APX-hard for k = 3. We derive approximation algorithms achieving an approximation guarantee of 1.212 and 1.731 for k = 3 and k = 4, respectively. In both cases we provide a combinatorial algorithm and a randomized LP rounding algorithm. Moreover, we give a 2/3 k algorithm for general k.
Last, we consider the problem of multi-output AND or XOR function optimization on practical instances. We decompose the whole chip into gates with two inputs and apply De Morgan rules to make it consist of ANDs, XORs and inverters only. We then collect single-output AND and single-output XOR functions implemented on the chip and combine them to a larger instance whenever they share at least two inputs. Afterward, we introduce an integer linear program similar to the rounded LP introduced in our theoretical work and solve it using an ILP solver to decrease the number of gates in the instances. This algorithm is then followed by a technology mapping and some other restructuring routines. We present tests on the EPFL logic benchmark instances as well as on industry chips provided by our industry partner IBM and show experimental results and different statistics. Even though there is some distortion by technology mapping, the results show that our core algorithm is useful and can reduce the number of gates significantly.},
url = {https://hdl.handle.net/20.500.11811/14213}
}
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