Data Handling Processor and Signal Transmission in the Belle II DEPFET Pixel Detector

Abstract

The high precision measurements at the B factories have generated a new insight of the Standard Model with respect to CP violation and delivered higher constraints on the Standard Model parameters, i.e. CKM matrix. The upgrade of the asymmetric electron-positron collider KEKB in Japan to SuperKEKB introduces new challenges as the luminosity increases by a factor 40. The high luminosity forces the inclusion of a highly segmented detector, i.e. pixel detector, close to the interaction point, in order to improve the vertex resolution. The result is a complete new detector, Belle II. Due to the integrated pixel<br /> sub-detector the total data rate of Belle II increases 50 fold. The newly introduced pixel sub-detector generates roughly 95% of the total data. Thus online data reduction is inevitable to cope with the amount of data sent to the back-end of the detector system. This thesis investigates the capability of the on-module<br /> ASIC to cope with the high data rates, i.e. 1.6 Gbps, and proves that the transmission line system of the pixel detector is sufficiently designed to guarantee high signal integrity over approx. 3 m of transmission.<br /> The Data Handling Processor on the pixel modules is designed to handle, reduce the pixel data generated in the pixel array of the module and to transmit them to the back-end system.