An FPGA-based Sampling ADC for the Crystal Barrel Calorimeter

Abstract

The CBELSA/TAPS experiment in Bonn investigates the excitation spectra of protons and neutrons through meson-photoproduction. With its ability to polarize the target nucleons and the incident photon beam, the experiment has contributed significantly to a better understanding of the baryon excitation spectrum, and with that also to the understanding of the strong interaction in the non-perturbative regime. Since a recent upgrade, the experiment's main electromagnetic calorimeter, the Crystal Barrel, is read out by avalanche photo-diodes. Their signal is digitized by integrating Fastbus ADCs, providing a value proportional to the energy deposited in the calorimeter crystals. As a result of long conversion and transfer times, those ADCs have become the limiting factor in the data acquisition, with possible readout rates of less than 2 kHz. Moreover, the possibility to identify pile-up, i.e. quickly-succeeding energy deposits that overlap in the integration window, is presently missing. <br /> Already years ago, it has been investigated whether this readout system could be replaced by faster and more modern sampling ADCs, which offer access to the waveform representation for a more sophisticated analysis, but the investigations were limited to commercially available digitizers with high cost and low channel densities. In addition, the firmware (operating system) of such digitizers is usually closed-source, which does not allow for the implementation of experiment-specific algorithms. Due to the above reasons, the investigations had not led to a satisfactory solution, and the Fastbus ADCs are still in operation today. <br /> In this thesis, the development and test of a custom (non-commercial) FPGA-based sampling ADC, which will replace the Fastbus ADC, has been driven forward. This so-called CB-SADC (Crystal Barrel Sampling Analog-to-Digital Converter) has been adapted from a prototype of the PANDA experiment in such a way that it is suited to operate within the specific conditions of the CBELSA/TAPS experiment. <br /> Apart from the hardware development, the firmware for the FPGA, which processes the digitized data, was designed and tested extensively. Specific algorithms allow not only the determination of the deposited energy and the timestamps of each event, but also an event-wise baseline determination and the detection of pile-up events. An online correction of pileup events, which occur with significant frequency in the forward region of the calorimeter, leads to a higher data quality and improved efficiency and statistics. <br /> Apart from the hardware development, the firmware for the FPGA, which processes the digitized data, was designed and tested extensively. Specific algorithms allow not only the determination of the deposited energy and the timestamps of each event, but also an event-wise baseline determination and the detection of pile-up events. An online correction of pileup events, which occur with significant frequency in the forward region of the calorimeter, leads to a higher data quality and improved efficiency and statistics. <br /> Two prototype iterations of the CB-SADC have been produced and were tested thoroughly in the laboratory and in connection with the CBELSA/TAPS experiment. The results of those tests, and preliminary analyses of production beam times with 50% of the calorimeter's forward half being read out by the CB-SADCs, showed an improvement of the data quality. The timestamp determination of the CB-SADCs in the energy regime below 10MeV has provided data where the experiment's TDC (Time-to-Digital Converter) either has worse resolution or cannot provide timestamps at all. In addition, standalone tests in the laboratory and tests with the data acquisition system have confirmed a much higher readout speed compared to the integrating Fastbus ADCs. Based on the achieved results, it was finally decided to equip the whole calorimeter with the new CB-SADC readout. <br /> At the time of finalizing this thesis, all CB-SADCs have been produced and are prepared for installation in the experimental hall. They will be running in parallel with the integrating Fastbus ADCs during the next production beam times, offering an opportunity to test the CB-SADC readout system as a whole. As soon as it is proven that the new readout works reliably, the limiting integrating Fastbus ADCs will be decommissioned and the CBELSA/TAPS experiment can start taking data with an increased readout rate.